A recent leak has shed light on the alleged specifications of AMD’s highly anticipated Zen 5 architecture. According to sources, the next-generation CPU design is poised to bring substantial improvements over its predecessor, Zen 4, with a reported 10 to 15% increase in Instructions Per Clock (IPC).
The leak, originating from the YouTube channel “Moore’s Law Is Dead,” discloses key details about Zen 5’s core architecture. Notably, the L1 cache, branch predictor, execution window, and core processing throughput are expected to see significant enhancements. The branch predictor is said to have received notable upgrades including zero bubble conditional branches, heightened accuracy, and an expanded Branch Target Buffer (BTB). Additionally, Zen 5 is slated to feature a larger L1 cache, up from 32KB in Zen 4 to 48KB.
Improvements in the chip’s throughput are anticipated as well. This includes the incorporation of two basic block fetch units, eight wide-dispatch/rename units, six Arithmetic Logic Units (ALUs), four load units, two store units, and other enhancements. The scheduler, responsible for managing instruction execution, is reported to have a larger structure size.
Furthermore, the integer scheduler is expected to be both larger and more unified compared to previous designs. While additional data prefetching enhancements are mentioned, specific details remain undisclosed.
A noteworthy revelation from the leaked information pertains to Zen 5’s core complexes, known as CCXs. These are set to double in core count from eight to sixteen, marking a significant advancement since Zen 2. This development suggests the potential emergence of processors with up to 32 cores, potentially bearing the moniker “Ryzen 9 8950X.”
Despite these exciting revelations, details about the specific types of cores within the Zen 5 core clusters remain undisclosed. It remains uncertain whether half of the core count will be allocated to Zen 5c efficiency cores, or if the entire stack will consist of vanilla Zen 5 performance cores. A combination of both scenarios is also plausible, given AMD’s indication of various models with FP-512 support and some featuring low-power cores.
It’s important to clarify that the leaked slides primarily pertain to AMD’s enterprise server chips (EYPC) and may not directly translate to mainstream consumer desktop CPUs. Therefore, certain features, such as FP-512 support, may not necessarily find their way into the expected Ryzen 8000 series chips.
In addition to Zen 5, the leak also provides insights into AMD’s Zen 6 architecture. The slides suggest an estimated minimum 10% improvement in IPC, the introduction of FP16 support for AI and machine learning applications, and the inclusion of a new memory profiler. Notably, AMD is projected to double core counts per Compute Complex Die (CCD) from 16 to 32 cores in Zen 6, potentially integrating slower or more compact Zen 6 efficiency cores. Zen 5 is anticipated to make its debut in 2024 alongside AMD’s Ryzen 8000-series desktop and mobile processors. However, it’s crucial to approach this information with a degree of skepticism, given the preliminary nature of the leak and the time remaining until an official release. The reported enhancements, if accurate, signify a promising stride forward for AMD’s CPU technology.