Intel, a leader in semiconductor technology, has unveiled the highly anticipated 6th Generation Xeon Scalable ‘Granite Rapids’ processors, marking a significant leap in computational power. These multi-tile datacenter CPUs are set to revolutionize the industry when they hit the market in the first half of 2024.
Simultaneously, an anonymous hardware source, Yuuki_AnS, leaked specifications of the ES1 samples of these processors.
The Granite Rapids processor introduces an innovative disaggregated design, incorporating five chiplets. Among these, three tiles house Performance cores, each equipped with 2MB of L2 cache, 4MB of L3 cache, and four DDR5 interfaces. Complementing these, two high-speed input/output (HSIO) tiles ensure seamless data transmission.
These Granite Rapids CPUs are projected to support an impressive 12 DDR5 memory channels, compatible with DDR5-6400 and MCR DIMMs. Additionally, they will feature a substantial 136 PCIe Gen5 lanes, with robust CXL 2.0 support, and the capacity for up to six UPI links.
While Intel has yet to confirm the core count officially, leaked ES1 samples provide a tantalizing peek. These samples, boasting an eight-channel memory subsystem (equivalent to two chiplets), hint at a potential maximum of 56 cores, supported by a generous 288MB of cache. This suggests that each tile may house either 28 or 30 cores, with two cores per chiplet potentially reserved for redundancy.
The production models of Granite Rapids CPUs are expected to push the boundaries even further, potentially offering an astounding 84 to 90 cores. Notably, the clock speeds, ranging from 1.10 GHz to 2.70 GHz, apply specifically to engineering samples.
Intel employs Intel 3 (3nm-class) process technology for the compute chiplets, while the HSIO chiplets are manufactured on a 7nm-class node. This strategic approach, grounded in proven technology, strikes an optimal balance between performance and cost efficiency, particularly for modern I/O chiplets.
Visually, images released by Intel strategically showcase the arrangement of components. The two HSIO dies are positioned at the top and bottom, flanking the compute dies nestled in the middle. These elements are intricately connected through an unspecified number of EMIB (Embedded Multi-Die Interconnect Bridge) links seamlessly integrated into the substrate.
Intel’s Granite Rapids platform is engineered to accommodate a dynamic range of one to eight sockets within a single server, underscoring Intel’s commitment to versatility and scalability. Currently, Intel is in the process of providing samples of the 8S-capable Granite Rapids CPU, reaffirming the company’s dedication to pushing the boundaries of computing capabilities. With these monumental advancements, Intel is poised to reshape the landscape of high-performance computing.