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Intel Core Ultra “Meteor Lake” CPU Die Shots Give A Closer Look At Various CPU, GPU & IO Chiplets

Intel enthusiasts and tech aficionados are abuzz with excitement as die shots of Intel's highly...

Intel Core Ultra “Meteor Lake” CPU Die Shots Give A Closer Look At Various CPU, GPU & IO Chiplets

Intel enthusiasts and tech aficionados are abuzz with excitement as die shots of Intel’s highly anticipated Core Ultra “Meteor Lake” CPUs have emerged, offering an intricate glimpse into the architecture’s inner workings. Shared by HXL (@9559pro), these die shots provide an unprecedented close-up of the various chiplets that constitute the Meteor Lake CPUs, shedding light on the CPU, GPU, and IO components in intricate detail.

Meteor Lake CPUs are built upon a disaggregated architecture, a strategic move by Intel to amalgamate diverse Intellectual Properties (IPs) within chiplets, arranged in a chiplet-esque fashion. HXL’s die shots allow enthusiasts to explore the chiplet (Tile) layout, presenting a more detailed perspective compared to the 3D renders initially published by Intel.

Comprising four chiplets in total, Meteor Lake incorporates Compute (CPU), Graphics (GPU), SOC (System on a Chip with components like NPUs), and I/O tiles. This innovative design marks Intel’s foray into the chiplet ecosystem within the client segment, a significant step forward in processor technology.

A distinctive feature of Meteor Lake is the utilization of both internal and external fabrication processes. While Intel handles some of the tiles, third-party fabs like TSMC contribute to the manufacturing process. The main CPU tile adopts the “Intel 4” or 7nm EUV process node, showcasing Intel’s commitment to cutting-edge technology. In contrast, the SOC Tile and IO Tile leverage TSMC’s 6nm process node (N6), indicating collaboration and diversity in the manufacturing process.

The GPU tile, a pivotal component of Meteor Lake CPUs, features a 4 Xe-Core variant based on the Arc Akchemist architecture. TSMC’s 5nm process node is employed for the GPU, underscoring Intel’s pursuit of performance and efficiency in graphical processing.

To provide a more tangible understanding, the die shots were taken from a 2+8+2 SKU configuration, consisting of 2 P-Cores based on Redwood Cove, 8 E-Cores based on Crestmont, and 2 additional low-power E-Cores. The CPU tile reveals the arrangement of these cores, with the cache occupying a prominent position. In this specific configuration, there is a total of 12 MB of Smart Cache, distributed among the Redwood Cove P-Cores and Crestmont E-Cores as per Locuza’s die-shot analysis.

Moving beyond the CPU tile, the GPU tile showcases the intricacies of the 4 Xe-Core variant. However, the SOC and I/O tiles steal the spotlight with their diverse components, including controllers for Memory, Storage, and PCIe, NPUs, and a dedicated low-power island for Video. The SOC tile further incorporates two Crestmont LP E-Cores, highlighting the complexity and versatility of Meteor Lake’s design.

In addition to the comprehensive die shots, the article provides insights into a dummy spacer die used for thermal testing. This dummy die has been a source of confusion for some, as it was designed specifically for testing thermal envelopes in configurations like 2+8 and 6+8 SKUs. Die size analyses by OneRaichu & Andreas Schilling estimate sizes for the Compute tile (69.67mm2), SOC tile (100.15mm2), GPU tile (44.25mm2), and IO tile (27.42mm2), offering a quantitative perspective on the physical dimensions of Meteor Lake’s architecture.

As the die shots continue to captivate the tech community, enthusiasts eagerly anticipate annotated versions that promise even deeper insights into the intricacies of Intel’s Core Ultra “Meteor Lake” CPUs. The die shots, surpassing the allure of 3D renders, mark a pivotal moment in Intel’s technological journey and pave the way for a new era of chiplet-based processors.

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